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>rosenbridge coprocessor

the via CPU is a RISC CPU at its heart

and the alternate instruction set was documented

· SubwayTooter · 0 · 3 · 4

@Elizafox tbh a lot of modern processors *are* like that

the C3 was crazy enough to let you twiddle inside of it

@calvin yeah if you set the ALTINST MSR to 1, which some broken BIOSes probably do. The mitigation is shit simple.

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